Machine Instruction
Q1.
A computer which issues instructions in order, has only 2 registers and 3 opcodes ADD, SUB and MOV. Consider 2 different implementations of the following basic block :\begin{array}{l|l} \text { Case } 1 & \text { Case } 2 \\ \hline t 1=a+b ; & t 2=c+d \\ t 2=c+d ; & t 3=e-t 2 \\ t 3=e-t 2 ; & t 1=a+b \\ t 4=t 1-t 2 ; & t 4=t 1-t 2 \end{array}Assume that all operands are initially in memory. Final value of computation also has to reside in memory. Which one is better in terms of memory accesses and by how many MOV instructions?Q2.
Consider the given C-code and its corresponding assembly code, with a few operands U1-U4 being unknown. Some useful information as well as the semantics of each unique assembly instruction is annotated as inline comments in the code. The memory is byte-addressable.Which one of the following options is a CORRECT replacement for operands in the position (U1, U2, U3, U4) in the above assembly code?Q3.
Consider the following instruction sequence where registers R_1,R_2 \text{ and }R_3 are general purpose and MEMORY[X] denotes the content at the memory location X.\begin{array}{llc} \textbf{Instruction} & \textbf{Semantics} & \textbf{Instruction Size} \text{ (bytes)} \\ \hline \text{MOV } R1, (5000) & R1 \leftarrow \text{MEMORY}[5000] & 4 \\ \hline \text{MOV } R2, (R3) & R2 \leftarrow \text{MEMORY}[R3] & 4 \\ \hline \text{ADD} R2, R1 & R2 \leftarrow R1 + R2 & 2 \\ \hline \text{MOV } (R3), R2 & \text{MEMORY}[R3] \leftarrow R2 & 4 \\ \hline \text{INC } R3 & R3 \leftarrow R3+1 & 2 \\ \hline \text{DEC } R1 & R1 \leftarrow R1-1 & 2 \\ \hline \text{BNZ } 1004 & \text{Branch if not zero to the} & 2 \\ & \text{given absolute address} \\ \hline \text{HALT} & \text{Stop} & 1 \\ \hline \end{array} Assume that the content of the memory location 5000 is 10, and the content of the register R_3 is 3000. The content of each of the memory locations from 3000 to 3020 is 50. The instruction sequence starts from the memory location 1000. All the numbers are in decimal format. Assume that the memory is byte addressable. After the execution of the program, the content of memory location 3010 is ____________Q4.
Consider a 32- bit processor which supports 70 instructions. Each instruction is 32 bit long and has 4 fields namely opcode, two register identifiers and an immediate operand of unsigned integer type. Maximum value of the immediate operand that can be supported by the processor is 8191. How many registers the processor has?Q5.
A data driven machine is one that executes an instruction if the needed data is available. The physical ordering of the code listing does not dictate the course of execution. Consider the following pseudo-code:A. Multiply E by 0.5 to get FB. Add A and B to get E C. Add B with 0.5 to get D D. Add E and F to get G E. Add A with 10.5 to get CAssume A,B,C are already assigned values and the desired output is G. Which of the following sequence of execution is valid?Q6.
Consider a processor with 64 registers and an instruction set of size twelve. Each instruction has five distinct fields, namely, opcode, two source register identifiers, one destination register identifier, and a twelve-bit immediate value. Each instruction must be stored in memory in byte-aligned fashion. If a program has 100 instructions, the amount of memory(in bytes) consumed by the program text is _____ .Q7.
A processor has 64 registers and uses 16-bit instruction format. It has two types of instructions: I-type and R-type. Each I-type instruction contains an opcode, a register name, and a 4-bit immediate value. Each R-type instruction contains an opcode and two register names. If there are 8 distinct I-type opcodes, then the maximum number of distinct R-type opcodes is _______.Q8.
Statements associated with registers of a CPU are given. Identify the false statement.Q9.
The contents of the flag register after execution of the following program by 8085 microprocessor will beProgram SUB A MVI B,(01)H DCR B HLTQ10.
A byte addressable computer has a memory capacity of 2^{m} K B(k \text { bytes }) and can perform 2^{n} operations. An instruction involving 3 operands and one operator needs maximum of: